1. Field of the Invention
The present invention relates to a method for forming data lines of a liquid crystal display, and more particularly, to a method for forming data lines of a liquid crystal display device that is capable of simplifying the stacking structure of data lines.
2. Description of the Background Art
In general, a liquid crystal display device displays a desired picture by individually supplying a data signal according to picture information to the liquid crystal cell arranged in a matrix form and controlling the light transmittance of the liquid crystal cells.
The liquid crystal display device includes a liquid crystal display panel on which liquid crystal cells of a pixel unit are arranged in a matrix form, and a drive integrated circuit (IC) for driving the liquid crystal cells.
The liquid crystal display panel includes a color filter substrate and a thin film transistor array substrate that face each other and a liquid crystal introduced between the color filter substrate and the thin film transistor array substrate.
On the thin film transistor array substrate of the liquid crystal display panel, there are a plurality of data lines for transmitting a data signal supplied from a data driver integrated circuit to the liquid crystal cell and a plurality of gate lines for transmitting a scan signal supplied from a gate driver integrated circuit to the liquid crystal cells. The liquid crystal cells are defined at each portion where the data lines and the gate lines cross each other.
The gate driver integrated circuit sequentially supplies a scan signal to the plurality of gate lines so that the liquid crystal cells arranged in a matrix form are sequentially selected line by line. A data signal is supplied from the data driver integrated circuit to the selected line of the liquid crystal cells.
A common electrode and a pixel electrode are formed with the color filter substrate and the thin film transistor array substrate facing each other for applying an electric field to the liquid crystal layer.
The pixel electrode is formed by liquid crystal cells on the thin film transistor array substrate, while the common electrode is integrally formed on the entire surface of the color filter substrate.
Accordingly, by controlling the voltage applied to the pixel electrode while a voltage is applied to the common electrode, the light transmittance of the liquid crystal cells can be individually controlled.
In order to control the voltage applied to the pixel electrode by each liquid crystal cell, a thin film transistor used as a switching device is formed at each liquid crystal cell.
With its merits of being thin and light, the liquid crystal display device has encroached on the next-generation monitor market in place of the CRT monitor, and as its adaptation coverage is being extended to television sets, a high resolution and large screen are a necessary demand for the device.
In order to meet the requirement of high resolution and large screen, development of a data line with a low resistance is a first requirement to minimize delay of a data signal.
However, since the line material, such as Cr, Mo or MoW, adopted for the liquid crystal display device has a high nonresistance, it can not be adopted for data lines, and thus a triple film structure of a lower buffer metal layer/aluminum layer/upper buffer metal layer is adopted.
The lower buffer metal layer is used to prevent the occurrence of a spiking phenomenon caused by the diffusion of aluminum portions of the aluminum layer, the main line, to the lower film, and the upper buffer metal layer is used to solve the contact resistance problem with a transparent electrode (ITO or IZO) which is in contact with the aluminum layer.
The conventional method for forming data lines of a liquid crystal display device will now be described in detail with reference to FIGS. 1A through 1D showing sequential sectional views thereof.
First, as shown in FIG. 1A, a gate electrode 2 is patterned on a TFT part of a glass substrate 1, and a SiNx film is formed as a gate insulation film 3 on the entire surface of the TFT part and the pad part.
Then, an amorphous silicon layer 4A and high concentration n+doping amorphous silicon layer 4B are sequentially formed at an upper portion of the gate insulation film 3 and patterned to form an active layer 4 aligned with the gate electrode 2 of the TFT part.
Next, a lower buffer metal layer 5, an aluminum layer 6 and an upper buffer metal layer 7 are sequentially formed on the entire upper portion of the resulting structure.
The buffer metal layer 5 is formed to prevent the occurrence of the spiking phenomenon caused as the aluminum layer 6, the main line, may diffuse to the lower film such as the active layer 4 and the gate insulation film 3, by utilizing a metal material such as Cr, Mo, MoW or Ti of Group VI or Group 3A of the periodic table.
The upper buffer metal layer 7 is formed to solve the contact resistance problem with the aluminum layer 6 and the transparent electrode 9 by utilizing the metal material such as Cr, Mo, MoW or Ti of the Group VI or Group 3A of the periodic table.
As shown in FIG. 1B, the lower buffer metal layer 5, the aluminum layer 6 and the upper buffer metal layer 7 stacked on the TFT part are patterned until the amorphous silicon layer 4A on the gate electrode 2 is exposed to separate source/drain regions, and at the same time, the buffer metal layer 5, the aluminum layer 6 and the upper buffer metal layer 7 are stacked on the pad part and patterned to form a triple data line.
As shown in FIG. 1C, a SiNx film is formed as an insulation film 8 on the entire upper surface of the resulting structure, and at the TFT part, the upper buffer metal layer 7 at the upper portion of the drain region is selectively etched to be partially exposed, and at the pad part, the upper buffer metal layer 7 of the data line is selectively etched to be partially exposed.
As shown in FIG. 1D, a transparent electrode 9 is formed on the entire upper surface of the resulting structure and then patterned to be in contact with the upper buffer metal layer 7 exposed on the TFT part and the pad part.
However, the data line forming method of a conventional liquid crystal display device, as described above, has the following problem, that is, in order to implement the low resistant data lines, the triple film structure with the stacked lower buffer metal layer/aluminum layer/upper buffer metal layer is adopted. However, the time required for the process of deposition and patterning is increased, causing a loss in yield and an increase in manufacturing cost.